1. Field of the Invention
The present invention relates to a semiconductor device and a method of fabricating a semiconductor device.
2. Description of Related Art
Trend for high integration on electronic devices has stimulated development of a semiconductor device (semiconductor package) such as a WLBGA (Wafer Level Ball Grid Array) including an external connecting terminal on one side and having approximately the same external dimensions as a semiconductor chip to be mounted. Otherwise, the WLBGA is occasionally called as Wafer Level Chip Size Package.
Such a semiconductor device is normally structured to expose one side (a side where a silicon substrate is formed) of semiconductor chips. Therefore, application of external force, for example, due to handling during an inspection step and an packaging step occasionally causes chipping such as cracking and breaking in ridge line portions of a semiconductor chip. In present specification, an end portion of one side of a semiconductor chip (for example, a ridge line portion 107 in FIG. 1) will be called a ridge line portion. A silicon piece generated by relevant chipping is adhered to a wiring layer and another semiconductor chip to cause deterioration in electrical property such as short circuit between mutual wirings, resulting in failure.
Japanese Patent Laid-Open No. 2006-80284 discusses technology for avoiding such a problem. As FIG. 11 illustrates, a semiconductor device 10 consists of a semiconductor chip 11 and external connecting terminals 13 over sealing resin 12. A chamfer portion 14 is formed in an end of the semiconductor chip 11. The chamfer portion 14 is intended to restrain occurrence of chipping during handling.
The object of Japanese Patent Laid-Open No. 2001-230224 is different. However, in order to improve strength of an entire semiconductor device against bending deformation, resin 15 with the same area as the area of the relevant semiconductor chip 11 is provided in structure on the semiconductor chip 11 and on the opposite side of the external connecting terminals 13 formed on a circuit surface 16 as in FIG. 12.